1. Field of the Invention
This invention relates to transistorized electrical circuitry and more particularly to a protective circuit for protecting high power transistors operated in parallel and at high frequencies.
2. Description of the Prior Art
In order to obtain high power at high frequencies, it is commonly necessary to parallel a plurality of transistors which are then operated as a composite group of like devices. This configuration can suffer catastrophic failure, however, when one of the transistors fails in a shorted condition because in a parallel circuit configuration all the bases are connected in parallel. The method heretofore used to protect the good transistors was to connect an electrical fuse in series with each base of all the transistors. Collector voltage (B+) was thus applied to all the bases when one of the transistors shorted until the fuse in the base of the shorted transistor blew. The elapsed time for clearing a fault, due to the nature of the fuse itself, was in the order of several milliseconds. However, due to the short length of "safe operating area" time for the remaining good transistors which is in the order of a few nanoseconds, the fuse will not operate sufficiently fast to prevent damage to the remaining transistors. The prior art protective schemes thus were adapted to protect the transistor to which the fuse was connected as opposed to protecting the balance of the remaining transistors from the failure of one transistor.
The applicant has conducted a preliminary patentability search and has developed the following references which are hereby made of record:
U.s. pat. No. 3,083,303, W.S. Knowles et al. PA1 U.s. pat. No. 3,490,031, I.R. Marcus et al. PA1 U.s. pat. No. 3,703,648, J.A. Wrabel. PA1 U.s. pat. No. 3,729,655, W. Gratzke.